module DE0Nano(
	input 	clk, 
	input 	reset,
	
	// SPI
	input 	spi_miso, 
	output 	spi_mosi, 
	output 	spi_sclk, 
	output 	spi_ss,
	
	// I2c
	inout		i2c_scl, 
	inout		i2c_sda,
	
	// EPCS Controller
	input 	epcs_miso,
	output 	epcs_mosi, 
	output 	epcs_sclk, 
	output 	epcs_ss,
	
	// SDRAM Controller
	output	[12:0] 	dram_addr,
	output	[1:0]		dram_ba,
	output				dram_cas,
	output				dram_cke,
	output				dram_clk,
	output				dram_cs,
	inout		[15:0]	dram_dq,
	output	[1:0]		dram_dqm,
	output				dram_ras,
	output				dram_we,
	
	// PIO_0
	output	[7:0]		pio_0,
	
	// PIO_1
	input		[7:0]		pio_1);
	
pll pll_inst(
	.inclk0				(clk),
	.c1					(dram_clk));

firmware firmware_inst(
	.clk_clk											(clk),
	.reset_reset_n									(reset),
	
	.spi_external_MISO							(spi_miso),
	.spi_external_MOSI							(spi_mosi),
	.spi_external_SCLK							(spi_sclk),
	.spi_external_SS_n							(spi_ss),
	
	.i2c_opencores_export_scl_pad_io			(i2c_scl),
	.i2c_opencores_export_sda_pad_io			(i2c_sda),
	
	.epcs_flash_controller_external_dclk	(epcs_sclk),
	.epcs_flash_controller_external_sce		(epcs_ss),
	.epcs_flash_controller_external_sdo		(epcs_mosi),
	.epcs_flash_controller_external_data0	(epcs_miso),
	
	.sdram_controller_wire_addr				(dram_addr),
	.sdram_controller_wire_ba					(dram_ba),
	.sdram_controller_wire_cas_n				(dram_cas),
	.sdram_controller_wire_cke					(dram_cke),
	.sdram_controller_wire_cs_n				(dram_cs),
	.sdram_controller_wire_dq					(dram_dq),
	.sdram_controller_wire_dqm					(dram_dqm),
	.sdram_controller_wire_ras_n				(dram_ras),	
	.sdram_controller_wire_we_n				(dram_we),
	
	.pio_0_external_connection_export		(pio_0),
	.pio_1_external_connection_export		(pio_1));
	
endmodule
